SPC5: an efficient SpMV framework vectorized using ARM SVE and x86 AVX-512

Evann Regnault1 and Bérenger Bramas2, 3

  1. Strasbourg University, UFR de Mathématique et d’Informatique
    7, rue René Descartes, 67084 Strasbourg, France
  2. Inria Nancy, CAMUS Team
    615 Rue du Jardin-Botanique, 54600 Villers-lès-Nancy, France
  3. ICube laboratory, ICPS Team
    300 bd Sébastien Brant, 67412 Illkirch Cedex, France


The sparse matrix/vector product (SpMV) is a fundamental operation in scientific computing. Having access to an efficient SpMV implementation is therefore critical, if not mandatory, to solve challenging numerical problems. The ARM-based AFX64 CPU is a modern hardware component that equips one of the fastest supercomputers in the world. This CPU supports the Scalable Vector Extension (SVE) vectorization technology, which has been less investigated than the classic x86 instruction set architectures. In this paper, we describe how we ported the SPC5 SpMV framework on AFX64 by converting AVX512 kernels to SVE. In addition, we present performance results by comparing our kernels against a standard CSR kernel for both Intel-AVX512 and Fujitsu-ARM-SVE architectures.

Key words

SpMV, vectorization, AVX-512, SVE

Digital Object Identifier (DOI)


Publication information

Volume 21, Issue 1 (January 2024)
Year of Publication: 2024
ISSN: 2406-1018 (Online)
Publisher: ComSIS Consortium

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How to cite

Regnault, E., Bramas, B.: SPC5: an efficient SpMV framework vectorized using ARM SVE and x86 AVX-512. Computer Science and Information Systems, Vol. 21, No. 1, 203–221. (2024), https://doi.org/10.2298/CSIS230819005R